Since 2021 our team has been listed every year in the “Top 100 Startups worth watching” in the EE Times, and our technology breakthroughs have been featured in The Telegraph, BBC and the New Statesman. Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We’re backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony Innovation Fund, Oxford Sciences Innovations, INKEF Capital and Octopus Ventures, and we have so far raised over £62 million in equity and grant funding. 

We bring together the brightest quantum engineers, integrated circuit (IC) engineers, quantum computing theoreticians and software engineers to create a unique, world-leading team, working together closely to maximise our combined expertise. Our collaborative and interdisciplinary culture is an ideal fit for anyone who thrives in a cutting-edge research and development environment focused on tackling big challenges and contributing to the development of scalable quantum computers based on silicon technology.

Our team of 100+ is based in Oxford and London, with a centre of mass in our Islington lab.

• Implement block-level and chip-level physical layouts for spin qubits in SiMOS quantum dots from concept through integration and tapeout using standard EDA tools.

• Drive layout work to completion using industry best practices to ensure manufacturability and scalability.

• Deliver layouts that meet agreed physical verification and sign-off criteria, and own tapeout readiness.

• Interpret EM analysis, adjusting layouts to meet reliability and integration goals.

• Create or adapt minimal schematics or netlists to support LVS and verification flows.

• Contribute to the definition and maintenance of PDKs, layout methodologies, conventions, and abstractions.

• Lead design reviews, tapeout planning, and technical documentation.

• Coach or manage layout engineers as the team grows.

• Collaborate closely with interdisciplinary teams, translating research intent into manufacturable layouts.

• Masters in Engineering, Physics, or related field, or equivalent professional experience.

• 6+ years leading chip layouts through tapeout in research-driven or novel technology environments.

• Strong proficiency with Cadence Virtuoso for full-chip and block-level layout and verification flows.

• Strong understanding of layout verification (DRC/LVS/ERC) using Calibre or equivalent.

• Experience interpreting EM simulation results to optimise layout for signal integrity and reliability.

• Proven ability to execute layouts evolving process nodes where formal design rules are incomplete and engineering judgment drives signoff decisions.

• Track record of effective cross-functional collaboration across disciplines and domains.

• Experience with quantum devices, CMOS process integration, and/or 3D integration.

• Experience developing PDKs, rule decks, or working closely with EDA teams.

• Scripting or automation experience (SKILL, Python, or similar).

• Experience managing a small team of layout engineers.

• Be part of a creative, world-leading team

• Competitive salary and share options scheme

• Contributory pension scheme

• Group private medical insurance scheme

• Life Assurance

Quantum Motion is committed to providing equal employment opportunity and does not discriminate based on age, sex, sexual orientation, gender identity, race, colour, religion, disability status, marital status, pregnancy, gender reassignment or any other protected characteristics covered by the Equality Act 2010.